Clock skew could cause failures in the combinational logic circuits. CLB can be configured as RAM. SRAM requires refresh PLDs consist of programmable combinational logic elements Maximum delay of the combinational circuit the connects the output of one register to the input of the other determines the operating clock frequency Adding more registers to the instruction set should not increase the instruction width Flip-Flops are typically not used in the implementation of memory systems because they are not fast enough A good design practice is to use non-blocking assignments when you are modeling both sequential and combinational logic The propagation time in a Flip-Flop needs to be larger than the hold time.